Logic circuit with single charge pulling out transistor and semiconductor integrated circuit using the same

ABSTRACT

A logic circuit performs a predetermined logic operation by supplying charge to an external load or putting out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area. Adjacent ones of the logic circuits have a common source diffusion layer so that the load capacitance with respect to the inverse signal can be significantly reduced, thus enabling the high speed operation.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates to logic circuits and semiconductorintegrated circuits using the same, and more particularly to logiccircuits which can be advantageously utilized in multiple inputcircuits, such as semiconductor memory decoder circuits, provided in anarray form, and semiconductor integrated circuits using theame.

[0003] (2) Description of the Related Art

[0004] As an example of the prior art multiple input logic circuit, atwo-input NAND circuit comprising a bipolar transistor and a MOStransistor (this structure being hereinafter referred to as BiCMOSstructure) will now be described. FIG. 1 is ircuit diagram showing theNAND circuit. As shown, the NAND circuit comprises a logic circuit stage1 having a CMOS transistor structure and an output stage 2 havingbipolar/MOS transistor 710 structure. Specifically, the logic circuitstage 1 includes a parallel circit of two p-channel MOS transistors M₂₃and M₂₄ and a series circuit of two n-channel MOS transistors M₂₁ andM₂₂, the parallel and series circuits being connected in series in thementioned order between a high potential power supply line 3 (at apotential V_(cc)) and a ground line 4. Of the two input signals A and Bsubjected to logical operation, the signal A is inputted to the gates ofthe p- and n-channel MOS transistors M₂₃ and M₂₁. The input signal B, onthe other hand, is inputted to the gates of the p- and n-channel MOStransistors M₂₄ and M₂₂. A signal which is produced as a result of theoperation, is outputted from the common node of the drains of the twop-channel MOS transistors and the n-channel MOS transistor M₂₁ andinputted to the output stage 2.

[0005] The output stage 2 includes bipolar transistor (hereinafterreferred to as BiP transistor) Q₂ and two n-channel MOS transistors M₂₅and M₂₆, these transistors being connected in series in the mentionedorder between the power supply line 3 and the ground line 4. The logicsignal from the logic circuit stage 1 is inputted to the base of thetransistor Q₂. The input signals A and B are also assigned to the gatesof the series n-channel MOS transistors M₂₅ and M₂₆, respectively. Thistwo-input NAND circuit having the BiCMOS structure provides its outputsignal X₀ from an output terminal 5, which is constituted by the nodalpoint between the drain of the n-channel MOS transistor M₂₅ and theemitter of the BiP transistor Q₂ in the output stage 2.

[0006] In the circuit shown in FIG. 1, when the signals A and B bothbecome “high”, the series n-channel MOS transistors M₂₁ and M₂₂ bothbecome “on”, while the parallel p-channel MOS transistors M₂₃ and M₂₄both become “off”. The base of the BiP transistor Q₂ is thus broughtdown to the ground potential so that this transistor is turned off. Atthis time, the series n-channel MOS transistors M₂₅ and M₂₆ also bothbecome “on” to cause the charge to a load (not shown) to be dischargedthrough them, thus pulling down the output signal X₀ to be “low”.

[0007] When either of the signals A and B becomes “low”, either of then-channel MOS transistors M₂₁ and M₂₂ becomes “off”, and thesetransistors thus cannot pull down the base potential on the BiPtransistor Q₂. Either of the p-channel MOS transistors M₂₃ and M₂₄, onthe other hand, is turned on, and these transistors thus pull up thebase potential on the BiP transistor Q₂. The BiP transistor Q₂ is thusturned on with its base potential pulled up to V_(cc). Since either ofthe series n-channel MOS transistors M₂₅ and M₂₆ is turned off at thistime, no charge is pulled through the output terminal 5. As the resultof charging by the BiP transistor Q₂, the output signal X₀ becomes“high”.

[0008] It is to be understood that the output X₀ of the circuit shown inFIG. 1 has the NAND logic such that it becomes “low” when a plurality ofinputs all become “high” and becomes “high” otherwise. The above logiccircuit is used frequently for decoder circuits assembled insemiconductor memories or the like. The circuit operation in such a caseis featured in that only one of a number of NAND gates in an arrayprovides a “low” output as a selected output while the other NAND gateoutputs are all “high” as non-selected outputs. The decoder circuit canfinally select a memory cell corresponding to an inputted address with aconnection of a plurality of stages of such NAND gates.

[0009] In the above NAND circuit, the output signal X₀ is pulled up to“high” by the BiP transistor Q₂ whose base current is supplied from atleast either one of the p-channel MOS transistors M₂₃ and M₂₄. Thus,high current capacity and high operation speed can be obtained. However,the output signal X₀ is pulled down by the pull-down of the basepotential on the BiP transistor Q₂ by the series n-channel MOStransistors M₂₁ and M₂₂ and also by the pullout of charge from theoutput load by the series n-channel MOS transistors M₂₅ and M₂₆. This isequivalent to doubling of the n-channel MOS transistor gate length andreduction to one half of the current capacity of the n-channel MOStransistor drain current. To compensate for the reduction to one half ofthe n-channel MOS transistor drain current, usually the gate width ofthe n-channel MOS transistors M₂₁, M₂₂, M₂₅ and M₂₆ is made large so asto increase the current capacity to prevent the speed-down of thepull-up as much as possible. However, by increasing the gate width, theinput capacitance viewed from the input signal is increased resulting ina delay in the operation of a preceding logic circuit stage (not shown).Where a plurality of logic gate stages are present, it is necessary forthe high speed operation of the circuit to improve the fan-outcharacteristic, i.e., the relation between the ratio of the inputcapacitance to the output load capacitance and the delay time, but thishas been seriously impeded by the capacity reduction of the seriesn-channel MOS transistors M₂₁, M₂₂, M₂₅ and M₂₅.

[0010] In the decoder circuit, the operation speed of the memory cellselection which is the purpose of the circuit, is greatly dependent onthe delay time in the selected signal output. The selection is effectedfor the pull-down of the output by the series n-channel MOS transistorsM₂₁ and M₂₂ and also M₂₅ and M₂₆ (or for the pull-up of the output byseries p-channel MOS transistors in a NOR circuit). Therefore, theoperation speed is greatly influenced by the reduction of the currentcapacity due to the series connection of MOS transistors.

SUMMARY OF THE INVENTION

[0011] An object of the invention, therefore, is to overcome theproblems existing in the prior art, and to provide a logic circuit inwhich the number of series connected MOS transistors constituting theroute for supplying charge to the load and pulling out charge therefromis reduced and which is capable of operating at a high speed and issmall in lay-out area.

[0012] Another object of the invention is to provide a logic circuitwhich is applicable to such circuits as semiconductor memory decodercircuits using a number of logic circuits disposed in an array and whichenables the high selection speed.

[0013] According to one aspect of the invention, there is provided alogic circuit performing a predetermined logic operation by supplyingcharge to an external load or pulling out charge therefrom according toa combination of the states of a plurality of externally inputted binarysignals, the logic circuit comprising:

[0014] at least a first transistor for supplying charge through anoutput terminal to the external load; and

[0015] at least a second transistor for pulling out the charge from theload through the output terminal,

[0016] one of the first and second transistors being constituted by aMOS field-effect transistor having a drain connected to the outputterminal,

[0017] the MOS field-effect transistor having a source receiving aninverse signal inverse to a signal combined for logic operation with aninput signal inputted to a gate of the MOS field-effect transistor.

[0018] The logic circuit may further comprises an inverse signalgenerating circuit for generating an inverse signal inputted to thesource of the MOS field-effect transistor,

[0019] the inverse signal generating circuit for generating the inversesignal, in which the logic amplitude thereof is reduced according to adown-threshold in two series n-channel MOS field-effect transistorsconnected between a power supply line and a reference potential point,by inputting complimentary signals in phase and in inverse phase withrespect to the inverse signal to the gates of the n-channel MOSfield-effect transistors, respectively.

[0020] According to another aspect of the invention, there is provided asemiconductor integrated circuit comprising a decoder circuit providedon a chip, the decoder circuit having an array of a plurality of logiccircuits performing a predetermined logic operation by supplying chargeto an external load or pulling out charge therefrom according to acombination of the states of a plurality of externally inputted binarysignals, each of the logic circuits comprising:

[0021] at least a first transistor for supplying charge through anoutput terminal to the external load; and

[0022] at least a second transistor for pulling out the charge from theload through the output terminal,

[0023] one of the first and second transistors being constituted by aMOS field-effect transistor having a drain connected to the outputterminal,

[0024] the MOS field-effect transistor having a source receiving aninverse signal inverse to a signal combined for logic operation with aninput signal to a gate of the MOS field-effect transistor,

[0025] the MOS field-effect transistor being arranged such that theadjacent ones of the logic circuits share a source diffusion layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of thepresent invention will be apparent from the following description ofpreferred embodiments of the invention explained with reference to theaccompanying drawings, in which:

[0027]FIG. 1 is a circuit diagram showing a prior art NAND circuit;

[0028]FIGS. 2A, 2B and 2C are respectively a circuit diagram, a truthtable and a layout pattern of a NAND circuit of a first embodimentaccording to the invention;

[0029]FIG. 3 is a circuit diagram showing a NAND circuit of a secondembodiment according to the invention;

[0030]FIG. 4 is a circuit diagram showing a NAND circuit of a thirdembodiment according to the invention;

[0031]FIG. 5 is a graph showing the relation between the delay time andthe number of elements in a prior art NAND circuit and a NAND circuithaving a BiCMOS structure embodying the invention;

[0032]FIG. 6 is a circuit diagram showing a NOR circuit of a fourthembodiment according to the invention;

[0033]FIG. 7 is a circuit diagram showing a NOR circuit of a fifthembodiment according to the invention;

[0034]FIG. 8 is a circuit diagram showing an AND circuit of a sixthembodiment according to the invention;

[0035]FIG. 9 is a circuit diagram showing an AND circuit of a seventhembodiment according to the invention;

[0036]FIG. 10 is a circuit diagram showing an AND circuit with aninverse signal generator of an eighth embodiment according to theinvention;

[0037]FIG. 11 is a circuit diagram showing an AND circuit of a ninthembodiment according to the invention;

[0038]FIG. 12 is a circuit diagram showing an OR circuit of a tenthembodiment according to the invention; and

[0039]FIG. 13 is a graph showing the relation between the delay time andthe C_(out)/C_(in) of a prior art AND circuit and AND circuits havingCMOS structure embodying the invention.

PREFERRED EMBODIMENTS OF THE INVENTION

[0040] Now, preferred embodiments of the invention are explained withreference to the drawings.

[0041]FIG. 2A is a circuit diagram showing a first embodiment of thelogic circuit according to the invention applied to a two-input NANDlogic circuit having the BiCMOS structure. Comparing FIGS. 2A and 1,this embodiment of the invention is significantly different from theprior art NAND circuit in that the current paths for pulling down outputstage BiP transistor base potential and pulling out charge from the loadare constituted by independent n-channel MOS transistors M₁₁ and M₁₄,respectively, instead of the series n-channel MOS transistors M₂₁ andM₂₂ and the series n-channel MOS transistors M₂₅ and M₂₆ in the priorart.

[0042] In this embodiment, an input signal A is inputted to the gate ofa p-channel MOS transistor M₁₂ as well as the gate of the n-channel MOStransistor M₁₁. The source of the p-channel MOS transistor M₁₂ isconnected to a high potential power supply line 3 (at V_(cc)). Aseparate input signal B is inputted to the gate of a p-channel MOStransistor M₁₃ which is parallel with the transistor M₁₁. The twop-channel MOS transistors have a common drain, which is connected to thebase of a BiP transistor Q₁ with the collector thereof connected to thepower supply line 3. The emitter of the BiP transistor Q₁ and the drainof the n-channel MOS transistor M₁₄, to which the signal A is a gateinput, are connected together, and this node is connected to an outputterminal 5. The inverse signal ∇B inverse to the input signal B isinputted to the sources of the n-channel MOS transistors M₁₁ and M₁₄ (∇Bhere and hereinafter is substituted for an upper bar indicating a signalinverted).

[0043] The logic operation of this embodiment will now be described withreference to the truth table shown in FIG. 2B. When the input signal Abecomes “low” (i.e., “0”), the n-channel MOS transistors M₁₁ and M₁₄ areturned off, while the p-channel MOS transistor M₁₂ is turned on. The BiPtransistor Q₁ is thus turned on with its base potential pulled up to thesupply voltage V_(cc) irrespective of the signal B. A large current isthus caused to flow from the collector to the emitter to charge the load(not shown) connected to the output terminal 5. The output X₀ thusbecomes “high” (i.e., “1”).

[0044] When the input signal A becomes “high”, the state of output X₀changes depending on the state of the input signal B. When the signal Bis “low” at this time, the inverse signal ∇B is “high”. The n-channelMOS transistors M₁₁ and M₁₄ are thus turned off. The p-channel MOStransistor M₁₂ is also turned off, but the other p-channel MOStransistor M₁₃ is turned on. As in the above case, the output X₀ thusbecomes “high”. When the input signal B is “high”, the n-channel MOStransistors M₁₁ and M₁₄ both become “on” since their gate and sourcepotentials become “high” and “low”, respectively. The p-channel MOStransistors M₁₂ and M₁₃, on the other hand, both become “off”. The BiPtransistor Q₁ is thus turned off with its base potential brought down tothe ground potential. The load is thus discharged by the “on” currentcapacity of the n-channel MOS transistor M₁₄, thus pulling down theoutput X₀ to the “low” level.

[0045] The transient response of this embodiment is featured by theoperation of input to the sources of the n-channel MOS transistors M₁₁and M₁₄ with the inverse signal ∇B. The source capacitance of then-channel MOS transistor M₁₄ used in this embodiment will now bedescribed. FIG. 2C is a layout pattern concerning the n-channel MOStransistor M₁₄ in the circuit shown in FIG. 2A. This layout patternassumes a decoder circuit of a semiconductor memory device. Where thereare four NAND gates NAND(1) to NAND(4) in an array, the layout of then-channel MOS transistor M₁₄ in each of the gates is as shown. Theinverse signal ∇B is shared by the four NAND gates. As the input signalA, signals A₁ to A₄ are each inputted to the gate of the n-channel MOStransistor M₁₄ in each of the NAND gates. In this case, it is importantthat a source diffusion layer is shared by the two NAND n-channel MOStransistors M₁₄ in two NAND gates. With this arrangement, thecapacitance of the source diffusion layer of the n-channel MOStransistor M₁₄ is reduced to one half. Particularly, with a device witha large side surface capacitance on the field side, it is reduced to beless than one half. With this structure of this embodiment, the inputcapacitance is reduced to about one half the usual gate inputcapacitance, thus improving the fan-out characteristics. In addition,the n-channel MOS transistor M₁₄ functions as a transfer gate and startspulling down the current from the output terminal 5 sooner than it isturned on by its gate input. It is thus possible to obtain a very fastoperation inclusive of the operation of a preceding stage logic circuit.

[0046] It has to be noted, however, that the load capacitance at theoutput terminal 5 is discharged through the line of the inverse signal∇B as an input signal, and the following condition (1) has to be met forthe fast operation.

Load capacitance at output terminal 5<Load capacitance with respect toinverse signal ∇B  (1)

[0047] When the load capacitance with respect to the inverse signal ∇Bis high, the influence of the discharge current from the output terminal5 is negligible. While the above example is the case when sourcediffusion layer is shared by adjacent NAND gates of n-channel MOStransistors M₁₄, the advantages of such a layout structure are alsoobtainable with n-channel MOS transistors M₁₁.

[0048] The response to the input of the signal A will now be considered.The sources of both the n-channel MOS transistors M₁₁ and M₁₄ areconnected to the ground line. That is, the output X₀ is pulled down bythe single stage n-channel MOS transistor. Thus, fast operation ispossible again. The input of the inverse signal ∇B to the n-channel MOStransistor source does not cause the source voltage to floatsignificantly so long as the above condition (1) of the load capacitanceratio of the output terminal 5 is being satisfied, and it is possible topull out the high n-channel MOS transistor current capacity.

[0049] In the case of an actual decoder circuit, the signal B and theinverse signal ∇B inverse thereto are or must be readily suppliedsimultaneously. In the case of four NAND circuits with two addresssignals inputted thereto, signals in phase with the two address signalsand the inverse signals inverse to the in-phase signals are inputsignals, and are necessarily present when a decoder circuit is assumed.In decoder circuits following a first decoder circuit, the inversesignals may not necessarily be present. Even in such a case, it isreadily possible to generate inverse signals for a plurality of NANDgates via an inverter stage. In this case, it is desirable to generatethe signal B which has a small load.

[0050] A second embodiment of the invention will now be described withreference to FIG. 3. In this embodiment, only a single p-channel MOStransistor M₃₂ is used for the pull-up of the base potential on anoutput stage BiP transistor Q₃. The p-channel MOS transistor M₃₂ isnormally held “on” with its gate held at the ground potential from aground line 4. The input signals are thus only the signal A and theinverse signal and, unlike in the preceding first embodiment, theinverse signal ∇B is unnecessary. This embodiment also has a lessernumber of elements than that in the first embodiment by one.

[0051] In this embodiment, in the other cases than when the signal A andthe inverse signal ∇B come up with “high” and “low”, respectively,p-channel MOS transistors M₃₁ and M₃₂ are “off”. Thus, the BiPtransistor Q₃ is held “on” with its base potential held pulled up to thesupply voltage V_(cc) by the p-channel MOS transistor M₃₂. As aconsequence, the Bip transistor Q₃ turns to an “on” state so that theoutput X₀ is made “high”. When the signal A and the inverse signal ∇Bare “high” and “low”, respectively, the n-channel MOS transistors M₃₁and M₃₃ both become “on”, and the output X₀ is pulled down to the “low”level by the current capacity of the n-channel MOS transistor M₃₃.

[0052] Since the p-channel MOS transistor M₃₂ is normally held “on”, thebase potential on the BiP transistor Q₃ is determined by the impedanceratio between the n- and p-channel MOS transistors M₃₁ and M₃₂. The BiPtransistor Q₃ thus can be turned off by setting such that its basepotential becomes lower than about 0.8 V which is the forward voltageacross its base-emitter p-n junction. In this case, no problem arises inthe “low” output. However, the size of the p-channel MOS transistor M₃₂cannot be made so large. This is so because the size determines the basepotential on the BiP transistor Q₃ in the “off” state thereof inaddition to the “on” capacity thereof. Therefore, the “high” output,i.e., the non-selected output of a decoder, is not provided so fast asin the first embodiment. The fan-out characteristic, however, is notsubstantially different since the input capacitance is reduced by thatcorresponding to a p-channel MOS transistor.

[0053] A third embodiment of the invention will now be described withreference to FIG. 4. Referring to the figure, this embodiment is thesame as the preceding embodiments in the point wherein the output X₀ ispulled down by using a single n-channel MOS transistor M₄₁. A feature ofthis embodiments resides in that the output X₀ is pulled up by usingonly BiP transistors. The inverse signal ∇B which is inputted to thesource of the n-channel MOS transistor M₄₁, is also inputted to the baseof the BiP transistor Q₄₁, and the inverse signal ∇A inverse to thesignal A is inputted to a base of a BiP transistor Q₄₂ which is parallelwith the transistor Q₄₁.

[0054] In this embodiment, when the signal A and the inverse signal ∇Bbecome “high” and “low”, respectively (i.e., A=1, B=1), the n-channelMOS transistor M₄₁ is turned on. At this time, the inverse signals ∇Aand ∇B both become “low”, and the two BiP transistors Q₄₁ and Q₄₂ areboth turned off to provide the output X₀ as a “low” output. In the othercases, the n-channel MOS transistor M₄₁ is “off”, while at least one ofthe BiP transistors Q₄₁ and Q₄₂ is turned on, so that the output X₀ ispulled up to the “high” level. In this embodiment, fast operation can beexpected, since the output pull-up BiP transistors Q₄₁ and Q₄₂ aredriven directly by the inverse signals ∇A and ∇B. However, since the BiPtransistor base capacitances can be seen from the input signals, thefan-out characteristic is not improved so much as in the precedingembodiments. However, the use of only three elements in this embodimentis a great merit in view of, for instance, the layout area on the chip.

[0055]FIG. 5 shows the performances of the first and third embodimentsof the invention in comparison with the performance of the prior artNAND circuit. In FIG. 5, the ordinate is taken for the delay time in theNAND circuit inclusive of the inverter connected thereafter, and theabscissa is taken for the number of elements in the NAND circuit. Thedelay time is taken by setting the ratio C_(out)/C_(in) of the outputload capacitance C_(out) to the input capacitance C_(in) to a constant,i.e., 20, from the consideration of the fan-out characteristic. As thedelay time, the average values of the two inputs when they arerespectively “high” and “low” are compared. The first embodiment haselements lesser by two than those in the prior art, while the delay timein this case is improved by nearly 20% from that in the prior art. Withthe third embodiment, the delay time is improved only by about 10% fromthat in the prior art, but the number of elements is reduced to be lessthan one half. Selection as to whether to attach importance to theoperation speed improvement or to the layout area reduction by reducingthe number of elements, may depend on the desired performance of theproduct to be designed.

[0056] A fourth embodiment of the invention will now be described withreference to FIG. 6. This embodiment is a two-input NOR circuit havingthe BiCMOS structure. Referring to FIG. 6, the base potential on a BiPtransistor Q₆ is pulled down by parallel n-channel MOS transistors M₆₂and M₆₃, to the gates of which input signals A and B are inputted.Transistors M₆₄ and M₆₅ are for pulling down an output X₁. For thepull-up of the base potential on the BiP transistor Q₆, a singlep-channel MOS transistor M₆₁ is provided, to the gate and source ofwhich the signal A and the inverse signal ∇B are inputted, respectively.In the prior art NOR circuit, this part is constituted by two seriesp-channel MOS transistors. In such a case, there is a problem in that,when providing the “high” output, the current capacity of the p-channelMOS transistors in the “on” state thereof is low and unable to supplysufficient base current to the transistor Q₆. In other words, thecapacity of the BiP transistor Q₆ cannot be made full use of, and it isnot readily enables the high speed operation. With this embodiment ofthe NOR circuit, like the case of the NAND circuit, the current capacityof the p-channel MOS transistor can be increased thus enabling the highspeed operation.

[0057] A fifth embodiment of the invention will now be described withreference to FIG. 7. Unlike the preceding fourth embodiment (see FIG.6), in this embodiment only a single n-channel MOS transistor M₇₂constitutes a base potential pull-down transistor on an output stage BiPtransistor Q₇. This n-channel MOS transistor M₇₂ is normally held “on”with its gate held at the supply voltage V_(cc) supplied from the powersupply line 3. In this circuit construction, the base potential on theBiP transistor Q₇ can be readily pulled up to the supply voltage V_(cc)so long as the n-channel MOS transistor M₇₂ can be turned off. In thisembodiment, since the transistor M₇₂ is normally held “on”, the basepotential on the transistor Q₇ is lower than the supply voltage V_(cc)by an amount corresponding to the impedance ratio between the p- andn-channel MOS transistors M₇₁ and M₇₂. This base potential reductionappears as a reduction of the output X₁, and it should be made to anextent that it does not deteriorate the circuit characteristics of thenext stage.

[0058] In the NOR circuit of the preceding fourth and fifth embodiment,the output of the p-channel MOS transistor M₇₁ which receives its inputat its source, is coupled to the base of the BiP transistor Q₇. Thus, ascompared to the NAND circuit, the condition (1) concerning the ratiobetween the output load capacitance and the load capacitance of theinverse signal ∇B which is a condition for the high speed operation, canbe readily attained. This is so because the output X₁ is changed via theBiP transistor Q₇. The operation speed, however, is not improved so muchas in the NAND circuit. In addition, since it is only a single p-channelMOS transistor that can receive the input thereto as the source, theelement number reduction effect is not so much as in the NAND circuit.

[0059] A sixth embodiment of the invention will now be described withreference to FIG. 8. This embodiment of the logic circuit is a CMOSstructure AND circuit, which comprises a NAND circuit and an inverterand does not use any BiP transistor. Referring to FIG. 8, input signalsA and B are assigned to the gates of parallel p-channel MOS transistorsM₈₂ and M₈₃, respectively. Also, the signal A and the inverse signal ∇Bare inputted to the gate and source, respectively, of the n-channel MOStransistor M₈₁. The drains of the p- and n-channel MOS transistors areconnected so as to constitute a common node, and a NAND output therefromis inputted to a CMOS inverter which includes a p- and an n-channel MOStransistor M₈₄ and M₈₅ in series with each other. The inverter output isthe output X₂ of the AND circuit.

[0060] In this embodiment, the NAND logic part is the same in thecircuit operation and characteristics as the previous NAND circuithaving the BiCMOS structure (i.e., the first embodiment shown in FIGS.2A to 2C). In this embodiment, however, the AND logic form comprisingthe NAND circuit and the CMOS inverter connected to the output side ofthe NAND circuit constitutes a basic unit. In the CMOS circuit, thedrive capacity with respect to the load is low compared to the BiCMCScircuit. Accordingly, for driving a large load, it is general to connecta drive inverter to a plurality of circuits, i.e., logic circuits. Thisway of driving is suitably adoptable for operations with an n-channelMOS transistor receiving the inverse signal ∇B at the source as well. Asalready described, for fast operation, it is necessary that the NANDoutput load capacitance be lower than the load capacitance with respectto the inverse signal ∇B. This requirement, however, may fail to besatisfied in the case of driving a large load of the output X₂ directlywith the NAND output. In a decoder circuit, its output is inputted to anumber of next stage logic circuits. Most of these circuits are notselected and, only in selected circuits, the NAND output load is seenthrough the source of the n-channel MOS transistor M₈₁. The output loadcapacitance of the NAND output part in this case is constituted by thesole driving CMOS inverter input capacitance. The load capacitance ofmost of the decoder outputs is thus the sum of the non-selected circuitside input capacitance and the inter-connection capacitance. It is thuspossible to readily meet the requirement for the fast operation, andhigh speed performance may be readily obtained.

[0061] A seventh embodiment of the invention will now be described withreference to FIG. 9. In this embodiment, a single p-channel MOStransistor M₉₂ which is normally held “on”, is used in lieu of thep-channel MOS transistors in the NAND circuit part of the CMOS structureAND circuit as in the above sixth embodiment, while a CMOS inverter isconnected to the NAND circuit to provide an AND output. With thisconstruction, when the n-channel MOS transistor M₉₁ is turned on, theNAND output is not lowered down to the ground potential but is slightlyfloated thereabove. When the extent of the floating is less than thethreshold voltage of a subsequent inverter stage n-channel MOStransistor M₉₄, however, no great through current will be caused. Ofcourse, a through current through the n-channel MOS transistor M₉₂ iscaused. However, this transistor is small in size and low in currentcapacity. In the case of a decoder circuit, the through current flowsthrough only selected circuits, which are extremely small number, sothat this does not pose any substantial problem.

[0062] An eighth embodiment of the invention will now be described withreference to FIG. 10. In the preceding seventh embodiment AND circuit(see FIG. 9), the inverse signal ∇B is supplied externally to the logiccircuit. This embodiment features that it includes a circuit forgenerating the inverse signal ∇B. In this embodiment, a plurality of ANDcircuits (outputs X₂₁ to X_(2n)) are driven by an inverse signalgenerator, which is a series connection of a pull-up n-channel MOStransistor M₁₀₃ and a pull-down n-channel MOS transistor M₁₀₄. Thisinverse signal generator functions as a push-pull type circuit to driveas signal line 6 of the inverse signal ∇B with signals ∇B₀ and B₀ inphase and in inverse phase respectively with the inverse signal ∇B beinginputted to the gates of the n-channel MOS transistors M₁₀₃ and M₁₀₄,respectively.

[0063] Of the MOS transistors in the AND circuit shown in FIG. 10, then-channel MOS transistor M₁₀₂, to the source of which the inverse signal∇B is inputted, is turned off when its source potential becomes lowerthan its gate potential by its threshold voltage V_(TH). This means thatin this embodiment the source potential on the n-channel MOS transistorM₁₀₂, i.e., “high” level of the inverse signal ∇B, need be pulled uponly to V_(cc)−V_(TH). The inverse signal ∇B is pulled up to the “high”level by the n-channel MOS transistor M₁₀₃, that is, it is pulled up tothe “high” level when the input signal ∇B₀ to the inverted signalgenerator becomes “high”. At this time, the “high” level of the outputsignal ∇B₀ that is obtained is V_(cc)−V_(TH) due to the “thresholdpull-down” in the n-channel MOS transistor M₁₀₃ although the “high”level of the input signal ∇B₀ is equal to the supply voltage V_(cc).This “high” level of the inverse signal ∇B coincides with the turn-offlevel of the AND logic part n-channel MOS transistor M₁₀₂. With theconstruction of this arrangement, it is possible to reduce the amplitudeof the inverse signal ∇B and obtain both the effects of speeding-up theoperation and reducing the current consumption. For example, assumingthe supply voltage V_(cc) to be 3.3 V, the delay time up to theappearance of the AND output can be reduced by about 20%, while thecurrent consumption can be reduced by about 30%. It is further possible,by an n-channel MOS transistor in lieu of the low current capacityp-channel MOS transistor for the inverse signal generator, to reduce thetransistor size and reduce the layout area of the inverse signal driveline buffer by about 25%.

[0064] A ninth embodiment of the invention will now be described withreference to FIG. 11. This embodiment is featured in that, as comparedwith the previous seventh embodiment, a p-channel MOS transistor M₁₁₃ isconnected in parallel with a p-channel MOS transistor M₁₁₂ which isnormally held “on”. The inverse signal inverse to the AND output X₂ isinputted to the gate of the p-channel MOS transistor M₁₁₃. When the NANDoutput is caused to go to “high” from “low” by this feed-back, thep-channel MOS transistor M₁₁₃ is turned on and cooperates with thetransistor M₁₁₂ to supply charge, thus quickly raising the NAND output.When the NAND output is pulled down from “high” to “low”, the p-channelMOS transistor M₁₁₃ is turned off and blocks current to an n-channel MOStransistor M₁₁₁. Thus, it has no influence on the NAND output pull-downspeed. The effect of the feed-back for the high speed operation isenhanced by setting the current capacity of the p-channel MOS transistorM₁₁₃ to be high with respect to the current capacity of the p-channelMOS transistor M₁₁₂. In this case, however, care should be taken for thefloating of the “low” level of the NAND output and the reduction of thecapacity of retaining the “high” level of this output.

[0065] A tenth embodiment of the invention will now be described withreference to FIG. 12. This embodiment is an OR gate, which comprises aNOR gate part having a series connection between a p-channel MOStransistor M₁₂₁ and an n-channel MOS transistor M₁₂₂, and an inverter 7for inverting the NOR output. As in the n-channel MOS transistor in theabove AND circuit (i.e., the seventh embodiment shown in FIG. 9), thesignal A is inputted to the gate of the p-channel MOS transistor M₁₂₁,while inputting the inverse signal ∇B to the source of this transistor.The p-channel MOS transistor M₁₂₁ is turned on when and only when thesignal A and the inverse signal ∇B are “low” and “high” (i.e., A=0,B=0), respectively. An output X₃ thus becomes “low” only at this time.Otherwise, the output X₃ is “high” since the p-channel MOS transistorM₁₂₁ is normally “off”. With this embodiment, as in the precedingembodiments, fast operation can be readily realized.

[0066]FIG. 13 shows the MOS transistor AND circuit fan-outcharacteristics of the prior art AND circuit and the embodiments of theinvention. In the figure, the ordinate is taken for the delay time, andthe abscissa is taken for C_(out)/C_(in) in the AND circuit comprisingthe NAND circuit and the inverter. The delay time as shown is theaverage delay time when the two inputs are inverted between “high” and“low”. Regarding the prior art AND circuit, values in the general CMOSstructure circuit are shown while, regarding the invention, values inthe AND circuits as the seventh and ninth embodiments are shown. It willbe seen from the figure that the operation is faster with theembodiments of the invention, particularly with the ninth embodimentincorporating the feed-back, than with the prior art circuitirrespective of the fan-out coefficients. Specifically, with the sameC_(out)/C_(in) the delay time can be reduced by about 30 to 40%.

[0067] As has been described in the foregoing, according to theinvention, the charge pull-out route in the NAND logic circuit which hasheretofore been constituted by a series connection of a plurality ofN-channel MOS transistors, is constituted by a single n-channel MOStransistor in which, in addition to a signal inputted to its gate, theinverse signal is directly inputted also to its source. The singlen-channel MOS transistor permits increasing the output pull-downcapacity. In the case of a BiCMOS NAND circuit, this construction can beadopted for both the output pull-down and the output stage bipolartransistor base potential pull-down to increase the operation speed,reduce the number of elements and reduce the layout area. In the case ofapplying the above structure to a CMOS NAND circuit, an AND circuittogether with an inverter is made to be a basic unit whereby the NANDoutput load capacitance with respect to the source input inverse signalline capacitance is reduced and the operation speed is increased.

[0068] Further increase of the operation speed and reduction of thepower consumption can be obtained by compressing the amplitude of thesource input inverse signal by the provision of a circuit for generatingthe inverse signal.

[0069] The invention is applicable to such logic circuits as NORcircuits and OR circuits as well as NAND circuits and AND circuits, andwhen applied particularly to semiconductor memory decoder circuits orthe like, it permits obtaining great effects of increasing the operationspeed, reducing the layout area and reducing the power consumption.

[0070] While the invention has been described in its preferredembodiments, it is to be understood that the words which have been usedare words of description rather than limitation and that changes withinthe purview of the appended claims may be made without departing fromthe true scope of the invention as defined by the claims.

What is claimed is:
 1. A logic circuit performing a predetermined logicoperation by supplying charge to an external load or pulling out chargetherefrom according to a combination of the states of a plurality ofexternally inputted binary signals, said logic circuit comprising: atleast a first transistor for supplying charge through an output terminalto said external load; and at least a second transistor for pulling outthe charge from said load through said output terminal, one of saidfirst and second transistors being constituted by a MOS field-effecttransistor having a drain connected to said output terminal, said MOSfield-effect transistor having a source receiving an inverse signalinverse to a signal combined for logic operation with an input signalinputted to a gate of said MOS field-effect transistor.
 2. The logiccircuit according to claim 1 , wherein said first and second transistorsare complementary MOS field-effect transistors.
 3. The logic circuitaccording to claim 1 , wherein said first or second transistor that isother than said MOS field-effect transistor is a bipolar transistor. 4.The logic circuit according to claim 2 , which further comprises abipolar/CMOS transistor structure which outputs an output signal of saidlogic circuit through an output stage constituted by a series circuit ofa bipolar transistor and a MOS field-effect transistor.
 5. The logiccircuit according to claim 3 , which further comprises a bipolar/CMOStransistor structure which outputs an output signal of said logiccircuit through an output stage constituted by a series circuit of abipolar transistor and a MOS field-effect transistor.
 6. The logiccircuit according to claim 1 , which further comprises an inverse signalgenerating circuit for generating an inverse signal inputted to thesource of said MOS field-effect transistor, said inverse signalgenerating circuit for generating said inverse signal, in which thelogic amplitude thereof is reduced according to a down-threshold in twoseries n-channel MOS field-effect transistors connected between a powersupply line and a reference potential point, by inputting complimentarysignals in phase and in inverse phase with respect to said inversesignal to the gates of said n-channel MOS field-effect transistors,respectively.
 7. The logic circuit according to claim 1 , which furthercomprises: a third transistor in parallel with said first transistor,said first transistor supplying charge to said load, a signal in phasewith respect to a logic output signal being fed-back to a controlelectrode of said third transistor.
 8. A logic circuit comprising: anoutput stage control transistor means having a drain; and a firstn-channel MOS field-effect transistor having a drain connected to saiddrain of said output stage control transistor means, said first inputsignal and the inverse signal inverse to said second input signal beinginputted to a gate and a source, respectively, of said first n-channelMOS field-effect transistor, the drains of said output stage controltransistor means and said first n-channel MOS field-effect transistorbeing connected as said common node connected to an output stage.
 9. Thelogic circuit according to claim 8 , in which said output stage controltransistor means comprises two parallel p-channel MOS field-effecttransistors receiving a first input signal and a second input signal,respectively.
 10. The logic circuit according to claim 8 , in which saidoutput stage comprises: a bipolar transistor having a collectorconnected to a high potential point, and a second n-channel MOSfield-effect transistor having a drain connected to an emitter of saidbipolar transistor, the drain of said first n-channel MOS field-effecttransistor being connected to a base of said bipolar transistor, saidnode of the emitter of said bipolar transistor and the drain of saidsecond n-channel MOS field-effect transistor being connected to anoutput terminal, said first input signal and the inverse signal inverseto said second input signal being inputted to a gate and a source,respectively, of said second n-channel MOS field-effect transistor. 11.The logic circuit according to claim 9 , in which said output stagecontrol transistor means comprises a p-channel MOS field-effecttransistor always being held “on” with the gate thereof held at aconstant potential.
 12. The logic circuit according to claim 10 , inwhich said output stage control transistor means comprises a p-channelMOS field-effect transistor always being held “on” with the gate thereofheld at a constant potential.
 13. A logic circuit comprising: twobipolar transistors having bases respectively receiving an inversesignal inverse to a first input signal and an inverse signal inverse toa second input signal; and an n-channel MOS field-effect transistorhaving a drain connected to a common node of emitters of said twobipolar transistors, said first input signal and said inverse signalinverse to said second input signal being inputted to a gate and asource, respectively, of said n-channel MOS field-effect transistor,said emitters of said two bipolar transistors and the drain of saidn-channel MOS field-effect transistor being connected as a common nodeto an output terminal.
 14. A logic circuit comprising: two paralleln-channel MOS field-effect transistors having gates respectivelyreceiving a first input signal and a second input signal; and a firstn-channel MOS field-effect transistor having a drain connected to acommon node of the drains of said n-channel MOS field-effecttransistors, said first input signal and the inverse signal inverse tosaid second input signal being inputted to a gate and a source,respectively, of said first p-channel MOS field-effect transistor, thedrains of said n-channel MOS field-effect transistors and said firstp-channel MOS field-effect transistor being connected as a common nodeconnected to an output stage.
 15. The logic circuit according to claim14 , in which said output stage comprises: a bipolar transistor having acollector connected to a high potential point; a third n-channel MOSfield-effect transistor having a drain thereof connected to an emitterof said bipolar transistor and a source connected to a referencepotential point; and a fourth n-channel MOS field-effect transistorconnected in parallel with said third n-channel MOS field-effecttransistor, said drain of said first p-channel MOS field-effecttransistor being connected to the base of said bipolar transistor, saidnode of the emitter of said bipolar transistor and the drains of saidthird and fourth n-channel MOS field-effect transistors being connectedto an output terminal, said first and second input signals beinginputted to the gates of said third and fourth n-channel MOSfield-effect transistors, respectively.
 16. A logic circuit comprising:an n-channel MOS field-effect transistor having a gate receiving a firstinput signal and a source and a drain respectively receiving an inversesignal inverse to a second input signal being inputted to the source andthe drain, respectively; and an output stage control transistor meanshaving a drain connected to the drain of said n-channel MOS field-effecttransistor, said common node of drains of said n-channel MOSfield-effect transistor and said output stage control transistor meansbeing coupled to an inverter having a CMOS transistor structure foroutputting an output signal.
 17. The logic circuit according to claim 16, in which said output stage control transistor means comprises twoparallel p-channel MOS field-effect transistors having gates receivingsaid first and second input signals, respectively.
 18. The logic circuitaccording to claim 16 , in which said output stage control transistormeans comprises a first p-channel MOS field-effect transistor beingalways held “on” with the gate thereof held at a constant potential. 19.The logic circuit according to claim 18 , which further comprises: asecond p-channel MOS field-effect transistor connected in parallel withsaid first p-channel MOS field-effect transistor, and structured suchthat a signal in phase with the signal from the drain of said n-channelMOS field-effect transistor is fed-back to the gate of said secondp-channel MOS field-effect transistor.
 20. The logic circuit accordingto claim 17 , which further comprises an inverse signal generatingcircuit for generating an inverse signal inputted to the source of saidn-channel MOS field-effect transistor, said inverse signal generatingcircuit for generating said inverse signal, in which the logic amplitudethereof is reduced according to a down-threshold in two series n-channelMOS field-effect transistors connected between a power supply line and areference potential point, by inputting complimentary signals in phaseand in inverse phase with respect to said inverse signal to the gates ofsaid n-channel MOS field-effect transistors, respectively.
 21. The logiccircuit according to claim 18 , which further comprises an inversesignal generating circuit for generating an inverse signal inputted tothe source of said n-channel MOS field-effect transistor, said inversesignal generating circuit for generating said inverse signal, in whichthe logic amplitude thereof is reduced according to a down-threshold intwo series n-channel MOS field-effect transistors connected between apower supply line and a reference potential point, by inputtingcomplimentary signals in phase and in inverse phase with respect to saidinverse signal to the gates of said n-channel MOS field-effecttransistors, respectively.
 22. The logic circuit according to claim 19 ,which further comprises an inverse signal generating circuit forgenerating an inverse signal inputted to the source of said n-channelMOS field-effect transistor, said inverse signal generating circuit forgenerating said inverse signal, in which the logic amplitude thereof isreduced according to a down-threshold in two series n-channel MOSfield-effect transistors connected between a power supply line and areference potential point, by inputting complimentary signals in phaseand in inverse phase with respect to said inverse signal to the gates ofsaid n-channel MOS field-effect transistors, respectively.
 23. Asemiconductor integrated circuit comprising a decoder circuit providedon a chip, said decoder circuit having an array of a plurality of logiccircuits performing a predetermined logic operation by supplying chargeto an external load or pulling out charge therefrom according to acombination of the states of a plurality of externally inputted binarysignals, each of said logic circuits comprising: at least a firsttransistor for supplying charge through an output terminal to saidexternal load; and at least a second transistor for pulling out thecharge from said load through said output terminal, one of said firstand second transistors being constituted by a MOS field-effecttransistor having a drain connected to said output terminal, said MOSfield-effect transistor having a source receiving an inverse signalinverse to a signal combined for logic operation with an input signal toa gate of said MOS field-effect transistor, said MOS field-effecttransistor being arranged such that the adjacent ones of said logiccircuits share a source diffusion layer.